This invention relates to semiconductor devices and the processing thereof and more particularly to III-V compound devices and a method of producing such field effect transistors.
With the advent of higher frequency semiconductor devices, especially in the field of gallium arsenide Field Effect Transistors (FET), there is a need for decreasing the source-to-gate resistance as well as the drain-to-gate resistance in order to more effectively operate at the higher frequency. Accordingly, the prior art methods of manufacturing gallium arsenide FET's which are to operate at these higher frequencies must be reviewed since these prior methods tend to produce devices that are frequency limited, i.e. they exhibit excessive amounts of resistance, inductance as well as capacitance. Especially in devices to be operted in the gigahertz portion of the spectrum and higher, the inductance associated with the gate, source and drain contacts must be carefully tailored in order to prevent any unnecessary frequency limiting inductance. Similarly, if the device is to be operated in the gigahertz portion of the radio frequency spectrum, the source-to-gate resistance as well as the drain-to-gate resistance must be maintained as low as possible.
One method of producing a gallium arsenide FET is described in my U.S. Pat. No. 4,266,333 which issued on May 12, 1981 entitled "METHOD OF MAKING A SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR" and assigned to the same assignee as the subject application. In my prior patent, a metal layer is first formed on a layer of gallium arsenide material and is subsequently defined to form spaced source and drain contacts. The structure is then covered with a thick layer of insulating material which is then masked and subjected to an isotropic etch. Thereafter, the gate member is deposited in the opening formed by the etch. While the above mentioned patent describes a viable method for producing gallium arsenide FET's the device so produced tends to have a limited upper frequency. Accordingly, I have devised the method of the subject application for producing a structure having reduced source-to-gate resistance as well as reduced drain-to-gate resistance and has the additional advantage of providing a very short gate contact. The net effect is to lower both the inductive and capacitive reactance and thus produce a device which will operate at higher frequencies than heretofore possible.